An output-capacitorless FVF-based low-dropout regulator for power management applications

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dc.contributor	Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica
dc.contributor	Universitat Politècnica de Catalunya. EPIC - Energy Processing and Integrated Circuits
dc.contributor.author	Shirmohammadli, V.
dc.contributor.author	Saberkari, Alireza
dc.contributor.author	Martínez García, Herminio
dc.contributor.author	Alarcón Cot, Eduardo José
dc.date	2016
dc.identifier.citation	Shirmohammadli, V., Saberkari, A., Martinez, H., Alarcon, E. An output-capacitorless FVF-based low-dropout regulator for power management applications. A: IEEE International Conference on Industrial Informatics. "2016 IEEE 14th International Conference on Industrial Informatics (INDIN): Palais des Congrès du Futuroscope, Futuroscope-Poitiers, France 19-21 July, 2016: proceedings". Futuroscope - Poitiers: Institute of Electrical and Electronics Engineers (IEEE), 2016, p. 258-263.
dc.identifier.citation	978-1-5090-2870-2
dc.identifier.citation	10.1109/INDIN.2016.7819169
dc.identifier.uri	http://hdl.handle.net/2117/101898
dc.language.iso	eng
dc.publisher	Institute of Electrical and Electronics Engineers (IEEE)
dc.rights	info:eu-repo/semantics/openAccess
dc.rights	http://creativecommons.org/licenses/by-nc-nd/3.0/es/
dc.subject	Àrees temàtiques de la UPC::Enginyeria electrònica
dc.subject	Àrees temàtiques de la UPC::Enginyeria elèctrica
dc.subject	Microelectronics
dc.subject	Low-dropout regulator
dc.subject	flipped voltage follower (FVF)
dc.subject	error amplifier
dc.subject	gain-bandwidth enhanced EA.
dc.subject	Microelectrònica
dc.title	An output-capacitorless FVF-based low-dropout regulator for power management applications
dc.type	info:eu-repo/semantics/publishedVersion
dc.type	info:eu-repo/semantics/conferenceObject
dc.description.abstract	This paper presents an output-capacitorless low dropout (LDO) regulator based on improved flipped voltage follower power stage for use in power management circuits. A new error amplifier (EA) structure, named as gain-bandwidth enhanced EA, is embedded in the LDO regulator. The LDO regulator is designed for the input and output voltages of 1.2 V and 1 V, respectively. Fast transients, low overshoot and undershoot, and low quiescent current of 6 µA are achieved for the proposed circuit. The LDO regulator is designed for maximum load current of 50 mA, achieving the current and power efficiencies of 99.99% and 83.3%, respectively. Additionally, up to 131 pF capacitance is used in the proposed LDO structure. The proposed circuit is designed and verified in HSPICE in TSMC 0.18 µm mixed signal CMOS process.
dc.description.abstract	Peer Reviewed

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