Low-quiescent current class-AB CMOS LDO voltage regulator

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dc.contributor	Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica
dc.contributor	Universitat Politècnica de Catalunya. EPIC - Energy Processing and Integrated Circuits
dc.contributor.author	Asefi, Saina
dc.contributor.author	Saberkari, Alireza
dc.contributor.author	Martinez-Garcia, H
dc.contributor.author	Alarcón Cot, Eduardo José
dc.date	2018
dc.identifier.citation	Asefi, S., Saberkari, A., Martinez-Garcia, H., Alarcon, E. Low-quiescent current class-AB CMOS LDO voltage regulator. A: IEEE International Symposium on Circuits and Systems. "2018 IEEE International Symposium on Circuits and Systems (ISCAS): proceedings: 27-30 May 2018: Florence, Italy". Institute of Electrical and Electronics Engineers (IEEE), 2018, p. 1-4.
dc.identifier.citation	978-1-5386-4881-0
dc.identifier.citation	10.1109/ISCAS.2018.8351006
dc.identifier.uri	http://hdl.handle.net/2117/126103
dc.language.iso	eng
dc.publisher	Institute of Electrical and Electronics Engineers (IEEE)
dc.relation	https://ieeexplore.ieee.org/document/8351006
dc.rights	info:eu-repo/semantics/openAccess
dc.subject	Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats
dc.subject	Integrated circuits
dc.subject	Class AB
dc.subject	Low quiescent current
dc.subject	Output capacitorless
dc.subject	CMOS integrated circuits
dc.subject	Electric current regulators
dc.subject	Capacitor-less
dc.subject	Class-AB
dc.subject	Envelope elimination and restorations
dc.subject	LDO voltage regulators
dc.subject	Low-dropout voltage regulators
dc.subject	Output capacitor
dc.subject	Output voltages
dc.subject	Quiescent currents
dc.subject	Voltage regulators
dc.subject	Circuits integrats
dc.title	Low-quiescent current class-AB CMOS LDO voltage regulator
dc.type	info:eu-repo/semantics/publishedVersion
dc.type	info:eu-repo/semantics/conferenceObject
dc.description.abstract	A low-quiescent current output-capacitorless class-AB CMOS low-dropout voltage regulator (LDO) capable to source/sink current to/from the load is presented, which is suitable for hybrid or linear-assisted structures utilized in envelope elimination and restoration (EER) applications. The proposed LDO regulator is designed and characterized in 0.18 µm CMOS process to provide a 1 V stable output voltage with 200 mV dropout without any off-chip output capacitor and can deliver a current range of 160 mA between -80 mA and +80 mA to the load, while consumes only 1.8 µA quiescent current.
dc.description.abstract	Peer Reviewed

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