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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
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dc.contributor | Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors |
dc.contributor | Universitat Politècnica de Catalunya. CERCLE - Cercle d'Arquitectura |
dc.contributor.author | Tabani, Hamid |
dc.contributor.author | Arnau Montañés, José María |
dc.contributor.author | Tubella Murgadas, Jordi |
dc.contributor.author | González Colás, Antonio María |
dc.date | 2018 |
dc.identifier.citation | Tabani, H., Arnau, J., Tubella, J., Gonzalez Colas, A. A novel register renaming technique for out-of-order processors. A: International Symposium on High-Performance Computer Architecture. "2018 IEEE International Symposium on High Performance Computer Architecture (HPCA 2018): Vienna, Austria; 24-28 February 2018". Institute of Electrical and Electronics Engineers (IEEE), 2018, p. 259-270. |
dc.identifier.citation | 978-1-5386-3660-2 |
dc.identifier.citation | 10.1109/HPCA.2018.00031 |
dc.identifier.uri | http://hdl.handle.net/2117/122264 |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.relation | https://ieeexplore.ieee.org/document/8327014 |
dc.relation | info:eu-repo/grantAgreement/ES/1PE/TIN2013-44375-R |
dc.relation | info:eu-repo/grantAgreement/ES/1PE/TIN2016-75344-R |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors::Arquitectures paral·leles |
dc.subject | High performance computing |
dc.subject | Precise exceptions |
dc.subject | Register file |
dc.subject | Register renaming supercomputers |
dc.subject | In-flight instructions |
dc.subject | Out-of-order processors |
dc.subject | Physical registers |
dc.subject | Precise exceptions |
dc.subject | Producer consumers |
dc.subject | Register files |
dc.subject | Register renaming |
dc.subject | Superscalar processor |
dc.subject | Computer architecture |
dc.subject | Càlcul intensiu (Informàtica) |
dc.title | A novel register renaming technique for out-of-order processors |
dc.type | info:eu-repo/semantics/publishedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
dc.description.abstract | |
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