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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
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dc.contributor | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.contributor.author | Falcón Samper, Ayose Jesús |
dc.contributor.author | Ramírez Bellido, Alejandro |
dc.contributor.author | Valero Cortés, Mateo |
dc.date | 2004 |
dc.identifier.citation | Falcón, A., Ramírez, A., Valero, M. A low-complexity, high-performance fetch unit for simultaneous multithreading processors. A: International Symposium on High-Performance Computer Architecture. "IEE Proceedings- Software". Madrid: Institute of Electrical and Electronics Engineers (IEEE), 2004, p. 244-253. |
dc.identifier.citation | 0-7695-2053-7 |
dc.identifier.citation | 10.1109/HPCA.2004.10003 |
dc.identifier.uri | http://hdl.handle.net/2117/113049 |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.relation | http://ieeexplore.ieee.org/document/1410081/ |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject | Parallel processing (Electronic computers) |
dc.subject | Simultaneous multithreading processors |
dc.subject | Processor scheduling |
dc.subject | Multi-threading |
dc.subject | Parallel architectures |
dc.subject | Pipeline processing |
dc.subject | Processament en paral·lel (Ordinadors) |
dc.title | A low-complexity, high-performance fetch unit for simultaneous multithreading processors |
dc.type | info:eu-repo/semantics/publishedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
dc.description.abstract | |
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