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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
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dc.contributor | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.contributor.author | Valero Cortés, Mateo |
dc.contributor.author | Peirón Guardia, Montse |
dc.contributor.author | Ayguadé Parra, Eduard |
dc.date | 1993 |
dc.identifier.citation | Valero, M., Peirón, M., Ayguadé, E. Access to streams in multiprocessor systems. A: Euromicro Workshop on Parallel and Distributed Processing. "Euromicro Workshop on Parallel and Distributed Processing: proceedings". Gran Canaria: Institute of Electrical and Electronics Engineers (IEEE), 1993, p. 310-316. |
dc.identifier.citation | 0-8186-3610-6 |
dc.identifier.citation | 10.1109/EMPDP.1993.336387 |
dc.identifier.uri | http://hdl.handle.net/2117/106627 |
dc.description.abstract | When accessing streams in vector multiprocessor machines, degradation in the interconnection network and conflicts in the memory modules are the factors that reduce the efficiency of the system. In this paper, we present a synchronous access mechanism that allows conflict-free access to streams in a SIMD vector multiprocessor system. Each processor accesses the corresponding elements out of order, in such a way that in each cycle the requested elements do not collide in the interconnection network. Moreover, memory modules are accessed so that conflicts are avoided. The use of the proposed mechanism in present-day architectures would allow conflict-free access to streams with the most common strides that appear in real applications. The additional hardware is described and is shown to be of a similar complexity as that required for access in order. |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.relation | http://ieeexplore.ieee.org/document/336387/ |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject | Multiprocessors |
dc.subject | Computer networks |
dc.subject | Multiprocessor interconnection networks |
dc.subject | Vector processor systems |
dc.subject | Multiprocessadors |
dc.subject | Ordinadors, Xarxes d' |
dc.title | Access to streams in multiprocessor systems |
dc.type | info:eu-repo/semantics/publishedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |