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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
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dc.contributor | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.contributor.author | Radojkovic, Petar |
dc.contributor.author | Cakarevic, Vladimir |
dc.contributor.author | Verdú Mulà, Javier |
dc.contributor.author | Pajuelo González, Manuel Alejandro |
dc.contributor.author | Cazorla Almeida, Francisco Javier |
dc.contributor.author | Nemirovsky, Mario |
dc.contributor.author | Valero Cortés, Mateo |
dc.date | 2013-12 |
dc.identifier.citation | Radojkovic, P., Cakarevic, V., Verdú, J., Pajuelo, M.A., Cazorla, F., Nemirovsky, M., Valero, M. Thread assignment of multithreaded network applications in multicore/multithreaded processors. "IEEE transactions on parallel and distributed systems", Desembre 2013, vol. 24, núm. 12, p. 2513-2525. |
dc.identifier.citation | 1045-9219 |
dc.identifier.citation | 10.1109/TPDS.2012.311 |
dc.identifier.uri | http://hdl.handle.net/2117/85462 |
dc.language.iso | eng |
dc.relation | http://ieeexplore.ieee.org/xpl/articleDetails.jsp?reload=true&arnumber=6338254 |
dc.relation | info:eu-repo/grantAgreement/MEDC/5PN/TIN2007-60625 |
dc.relation | info:eu-repo/grantAgreement/EC/FP7/287759/EU/High Performance and Embedded Architecture and Compilation/HIPEAC |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject | Multiprocessors |
dc.subject | Simultaneous multithreading processors |
dc.subject | Chip multithreading (CMT) |
dc.subject | Performance modeling |
dc.subject | Process scheduling |
dc.subject | Multiprocessadors |
dc.title | Thread assignment of multithreaded network applications in multicore/multithreaded processors |
dc.type | info:eu-repo/semantics/submittedVersion |
dc.type | info:eu-repo/semantics/article |
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