To access the full text documents, please follow this link: http://hdl.handle.net/2117/96823
dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
---|---|
dc.contributor | Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors |
dc.contributor.author | Quiñones, Eduardo |
dc.contributor.author | Parcerisa Bundó, Joan Manuel |
dc.contributor.author | González Colás, Antonio María |
dc.date | 2007 |
dc.identifier.citation | Quiñones, E., Parcerisa, Joan-Manuel, González, A. Improving branch prediction and predicated execution in out-of-order processors. A: International Symposium on High-Performance Computer Architecture. "2007 IEEE 13th International Symposium on High Performance Computer Architecture". Phoenix, AZ: Institute of Electrical and Electronics Engineers (IEEE), 2007, p. 75-84. |
dc.identifier.citation | 1-4244-0804-0 |
dc.identifier.citation | 10.1109/HPCA.2007.346186 |
dc.identifier.uri | http://hdl.handle.net/2117/96823 |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.relation | http://ieeexplore.ieee.org/document/4147649/ |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject | Compilers (Computer programs) |
dc.subject | Out of order |
dc.subject | Accuracy |
dc.subject | Instruction sets |
dc.subject | Computer aided instruction |
dc.subject | Degradation |
dc.subject | Registers |
dc.subject | Hardware |
dc.subject | Pipelines |
dc.subject | Proposals |
dc.subject | Costs |
dc.subject | Compiladors (Programes d'ordinador) |
dc.title | Improving branch prediction and predicated execution in out-of-order processors |
dc.type | info:eu-repo/semantics/publishedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
dc.description.abstract | |
dc.description.abstract |