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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
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dc.contributor | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.contributor | Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors |
dc.contributor.author | Llosa Espuny, José Francisco |
dc.contributor.author | Valero Cortés, Mateo |
dc.contributor.author | Ayguadé Parra, Eduard |
dc.contributor.author | González Colás, Antonio María |
dc.date | 1995 |
dc.identifier.citation | Llosa, J., Valero, M., Ayguadé, E., González, A. Hypernode reduction modulo scheduling. A: Annual IEEE/ACM International Symposium on Microarchitecture. "Proceedings of the 28th Annual International Symposium on Microarchitecture: November 29-December 1,1995, Ann Arbor, Michigan". Michigan: Institute of Electrical and Electronics Engineers (IEEE), 1995, p. 350-360. |
dc.identifier.citation | 0-8186-7349-4 |
dc.identifier.citation | 10.1109/MICRO.1995.476844 |
dc.identifier.uri | http://hdl.handle.net/2117/96797 |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.relation | http://ieeexplore.ieee.org/document/476844/ |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject | Linear programming |
dc.subject | Instruction scheduling |
dc.subject | Loop scheduling |
dc.subject | Software pipelining |
dc.subject | Register allocation |
dc.subject | Register spilling |
dc.subject | Programació lineal |
dc.title | Hypernode reduction modulo scheduling |
dc.type | info:eu-repo/semantics/publishedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
dc.description.abstract | |
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