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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
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dc.contributor | Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors |
dc.contributor | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.contributor.author | Abella Ferrer, Jaume |
dc.contributor.author | González Colás, Antonio María |
dc.contributor.author | Llosa Espuny, José Francisco |
dc.contributor.author | Vera Rivera, Francisco Javier |
dc.date | 2002 |
dc.identifier.citation | Abella, J., González, A., Llosa, J., Vera, X. Near-optimal loop tiling by means of cache miss equations and genetic algorithms. A: International Conference on Parallel Processing Workshops. "International Conference on Parallel Processing Workshops: 18-21 August 2002, Vancouver, B.C., Canada: proceedings". Vancouver: Institute of Electrical and Electronics Engineers (IEEE), 2002, p. 568-577. |
dc.identifier.citation | 0-7695-1680-7 |
dc.identifier.citation | 10.1109/ICPPW.2002.1039779 |
dc.identifier.uri | http://hdl.handle.net/2117/102559 |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.relation | http://ieeexplore.ieee.org/document/1039779/ |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject | Cache memory |
dc.subject | Genetic algorithms |
dc.subject | Performance evaluation |
dc.subject | Storage management |
dc.subject | Cache storage |
dc.subject | Memòria ràpida de treball (Informàtica) |
dc.subject | Algorismes genètics |
dc.title | Near-optimal loop tiling by means of cache miss equations and genetic algorithms |
dc.type | info:eu-repo/semantics/publishedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
dc.description.abstract | |
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