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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
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dc.contributor | Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors |
dc.contributor.author | Abella Ferrer, Jaume |
dc.contributor.author | Chaparro, Pedro |
dc.contributor.author | Vera Rivera, Francisco Javier |
dc.contributor.author | Carretero Casado, Javier |
dc.contributor.author | González Colás, Antonio María |
dc.date | 2010 |
dc.identifier.citation | Abella, J., Chaparro, P., Vera, X., Carretero, J., González, A. High-Performance low-vcc in-order core. A: International Symposium on High-Performance Computer Architecture. "HPCA-16 2010: The Sixteenth International Symposium on High-Performance Computer Architecture". Bangalore: Institute of Electrical and Electronics Engineers (IEEE), 2010, p. 1-11. |
dc.identifier.citation | 10.1109/HPCA.2010.5416630 |
dc.identifier.uri | http://hdl.handle.net/2117/102557 |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.relation | http://ieeexplore.ieee.org/document/5416630/ |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject | Microprocessors |
dc.subject | Frequency |
dc.subject | Random access memory |
dc.subject | Batteries |
dc.subject | Delay estimation |
dc.subject | Clocks |
dc.subject | Energy efficiency |
dc.subject | Voltage |
dc.subject | Phase estimation |
dc.subject | CMOS process |
dc.subject | Mobile handsets |
dc.subject | Microprocessadors |
dc.title | High-Performance low-vcc in-order core |
dc.type | info:eu-repo/semantics/publishedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
dc.description.abstract | |
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