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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
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dc.contributor | Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors |
dc.contributor.author | Topham, Nigel |
dc.contributor.author | González Colás, Antonio María |
dc.contributor.author | González González, José |
dc.date | 1997 |
dc.identifier.citation | Topham, N., González, A., González, J. The design and performance of a conflict-avoiding cache. A: Annual IEEE/ACM International Symposium on Microarchitecture. "MICRO 30: proceedings of the 30th Annual ACM/IEEE International Symposium on Microarchitecture". San Francisco: Institute of Electrical and Electronics Engineers (IEEE), 1997, p. 71-80. |
dc.identifier.citation | 0-8186-7977-8 |
dc.identifier.citation | 10.1109/MICRO.1997.645799 |
dc.identifier.uri | http://hdl.handle.net/2117/101279 |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.relation | http://ieeexplore.ieee.org/document/645799/ |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject | Cache memory |
dc.subject | Parallel processing (Electronic computers) |
dc.subject | Cache storage |
dc.subject | Memory architecture |
dc.subject | Performance evaluation |
dc.subject | Parallel machines |
dc.subject | Parallel architectures |
dc.subject | Performance evaluation |
dc.subject | Instruction sets |
dc.subject | Memòria ràpida de treball (Informàtica) |
dc.subject | Processament en paral·lel (Ordinadors) |
dc.title | The design and performance of a conflict-avoiding cache |
dc.type | info:eu-repo/semantics/publishedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
dc.description.abstract | |
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