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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
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dc.contributor | Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors |
dc.contributor.author | Bieschewski, Stefan |
dc.contributor.author | Parcerisa Bundó, Joan Manuel |
dc.contributor.author | González Colás, Antonio María |
dc.date | 2005 |
dc.identifier.citation | Bieschewski, S., Parcerisa, J.M., González, A. Memory bank predictors. A: IEEE International Conference on Computer Design. "2005 International Conference on Computer Design: 02-05 October 2005 San Jose, California: proceedings". San Jose, California: Institute of Electrical and Electronics Engineers (IEEE), 2005, p. 666-668. |
dc.identifier.citation | 0-7695-2451-6 |
dc.identifier.citation | 10.1109/ICCD.2005.73 |
dc.identifier.uri | http://hdl.handle.net/2117/100452 |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.relation | http://ieeexplore.ieee.org/document/1524223/ |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject | Cache memory |
dc.subject | Parallel processing (Electronic computers) |
dc.subject | Memory bank prediction |
dc.subject | Clustered microarchitectures |
dc.subject | Memòria ràpida de treball (Informàtica) |
dc.subject | Processament en paral·lel (Ordinadors) |
dc.title | Memory bank predictors |
dc.type | info:eu-repo/semantics/publishedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
dc.description.abstract | |
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