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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
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dc.contributor | Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors |
dc.contributor.author | Sánchez Navarro, F. Jesús |
dc.contributor.author | González Colás, Antonio María |
dc.date | 2000 |
dc.identifier.citation | Sánchez, F., González, A. Instruction scheduling for clustered VLIW architectures. A: International Symposium on System Synthesis. "Proceedings: The 13th International Symposium on System Synthesis". Madrid: Institute of Electrical and Electronics Engineers (IEEE), 2000, p. 41-46. |
dc.identifier.citation | 0-7695-0765-4 |
dc.identifier.citation | 10.1109/ISSS.2000.874027 |
dc.identifier.uri | http://hdl.handle.net/2117/100204 |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.relation | http://ieeexplore.ieee.org/document/874027/ |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject | Parallel processing (Electronic computers) |
dc.subject | Pipeline processing |
dc.subject | Scheduling |
dc.subject | Instruction sets |
dc.subject | Performance evaluation |
dc.subject | Program control structures |
dc.subject | Processament en paral·lel (Ordinadors) |
dc.title | Instruction scheduling for clustered VLIW architectures |
dc.type | info:eu-repo/semantics/publishedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
dc.description.abstract | |
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