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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
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dc.contributor | Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors |
dc.contributor.author | Aleta Ortega, Alexandre |
dc.contributor.author | Codina Viñas, Josep M. |
dc.contributor.author | Sánchez Navarro, F. Jesús |
dc.contributor.author | González Colás, Antonio María |
dc.date | 2001 |
dc.identifier.citation | Aleta, A., Codina, J.M., Sanchez, F., Gonzalez, A. Graph-partitioning based instruction scheduling for clustered processors. A: Annual IEEE/ACM International Symposium on Microarchitecture. "34th ACM/IEEE International Symposium on Microarchitecture, 2001, MICRO-34: proceedings". Austin: Institute of Electrical and Electronics Engineers (IEEE), 2001, p. 150-159. |
dc.identifier.citation | 0-7965-1369-7 |
dc.identifier.citation | 10.1109/MICRO.2001.991114 |
dc.identifier.uri | http://hdl.handle.net/2117/96793 |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.relation | http://ieeexplore.ieee.org/document/991114/ |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject | Microprocessors |
dc.subject | Processor scheduling |
dc.subject | Delay |
dc.subject | Energy consumption |
dc.subject | Job shop scheduling |
dc.subject | Digital signal processing |
dc.subject | Microarchitecture |
dc.subject | Transistors |
dc.subject | Wires |
dc.subject | VLIW |
dc.subject | Microprocessadors |
dc.title | Graph-partitioning based instruction scheduling for clustered processors |
dc.type | info:eu-repo/semantics/publishedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
dc.description.abstract | |
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