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dc.contributor | Universitat Politècnica de Catalunya. Departament de Ciències de la Computació |
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dc.contributor | Universitat Politècnica de Catalunya. ALBCOM - Algorismia, Bioinformàtica, Complexitat i Mètodes Formals |
dc.contributor.author | Cortadella, Jordi |
dc.contributor.author | Lupon Navazo, Marc |
dc.contributor.author | Moreno Vega, Alberto |
dc.contributor.author | Roca Pérez, Antoni |
dc.contributor.author | Sapatnekar, Sachin |
dc.date | 2016 |
dc.identifier.citation | Cortadella, J., Lupon, M., Moreno, A., Roca, A., Sapatnekar, S. Ring oscillator clocks and margins. A: IEEE International Symposium on Asynchronous Circuits and Systems. "22nd IEEE International Symposium on Asynchronous Circuits and Systems: 8-11 May 2016 Porto Alegre, Brazil: proceedings". Porto Alegre: Institute of Electrical and Electronics Engineers (IEEE), 2016, p. 19-26. |
dc.identifier.citation | 978-1-4673-9007-1 |
dc.identifier.citation | 10.1109/ASYNC.2016.14 |
dc.identifier.uri | http://hdl.handle.net/2117/96481 |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.relation | http://ieeexplore.ieee.org/document/7584887/ |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Enginyeria electrònica::Circuits electrònics |
dc.subject | Oscillators, Electric |
dc.subject | Asynchronous circuits |
dc.subject | Clocks |
dc.subject | Delay lines |
dc.subject | Phase locked loops |
dc.subject | Ring oscillator clocks |
dc.subject | Delay lines |
dc.subject | EDA machinery |
dc.subject | Timing analysis |
dc.subject | PLL |
dc.subject | Clock generator |
dc.subject | Oscil·ladors elèctrics |
dc.subject | Circuits asíncrons |
dc.title | Ring oscillator clocks and margins |
dc.type | info:eu-repo/semantics/submittedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
dc.description.abstract | |
dc.description.abstract |