To access the full text documents, please follow this link: http://hdl.handle.net/2117/91341
dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
---|---|
dc.contributor | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.contributor.author | Subasi, Omer |
dc.contributor.author | Unsal, Osman Sabri |
dc.contributor.author | Labarta Mancho, Jesús José |
dc.contributor.author | Yalcin, Gulay |
dc.contributor.author | Cristal Kestelman, Adrián |
dc.date | 2016 |
dc.identifier.citation | Subasi, O., Unsal, O., Labarta, J., Yalcin, G., Cristal, A. CRC-based memory reliability for task-parallel HPC applications. A: IEEE International Symposium on Parallel and Distributed Processing. "2016 IEEE International Parallel and Distributed Processing Symposium (IPDPS 2016): Chicago, Illinois, USA: 23-27 May 2016". Chicago, Illinois: Institute of Electrical and Electronics Engineers (IEEE), 2016, p. 1101-1112. |
dc.identifier.citation | 9781509021413 |
dc.identifier.citation | 10.1109/IPDPS.2016.70 |
dc.identifier.uri | http://hdl.handle.net/2117/91341 |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.relation | ieeexplore.ieee.org/document/7516107/ |
dc.relation | info:eu-repo/grantAgreement/ES/1PE/TIN2015-65316-P |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors::Arquitectures paral·leles |
dc.subject | Parallel processing (Electronic computers) |
dc.subject | Application programs |
dc.subject | Data flow analysis |
dc.subject | Error correction |
dc.subject | Errors |
dc.subject | Hardware |
dc.subject | Reconfigurable hardware |
dc.subject | Reliability |
dc.subject | Cyclic redundancy check |
dc.subject | Dataflow model |
dc.subject | Error correction capability |
dc.subject | Hardware acceleration |
dc.subject | Mathematical analysis |
dc.subject | Memory reliability |
dc.subject | Software-based solutions |
dc.subject | Task parallelism |
dc.subject | Processament en paral·lel (Ordinadors) |
dc.title | CRC-based memory reliability for task-parallel HPC applications |
dc.type | info:eu-repo/semantics/publishedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
dc.description.abstract | |
dc.description.abstract | |
dc.description.abstract |