Títol:
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Hardware-software coherence protocol for the coexistence of caches and local memories
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Autor/a:
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Álvarez Martí, Lluc; Vilanova, Lluís; González Tallada, Marc; Martorell Bofill, Xavier; Navarro, Nacho; Ayguadé Parra, Eduard
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Altres autors:
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Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors; Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
Abstract:
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Cache coherence protocols limit the scalability of multicore and manycore architectures and are responsible for an important amount of the power consumed in the chip. A good way to alleviate these problems is to introduce a local memory alongside the cache hierarchy, forming a hybrid memory system. Local memories are more power-efficient than caches and do not generate coherence traffic, but they suffer from poor programmability. When non-predictable memory access patterns are found, compilers do not succeed in generating code because of the incoherence between the two storages. This paper proposes a coherence protocol for hybrid memory systems that allows the compiler to generate code even in the presence of memory aliasing problems. Coherence is ensured by a software/hardware co-design where the compiler identifies potentially incoherent memory accesses and the hardware diverts them to the correct copy of the data. The coherence protocol introduces overheads of 0.26% in execution time and of 2.03% in energy consumption to enable the usage of the hybrid memory system, which outperforms cache-based systems by an speedup of 38% and an energy reduction of 27%. |
Abstract:
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Peer Reviewed |
Matèries:
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-Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors -Cache memory -Compilers (Computer programs) -Coherence protocol -Lcal memories -Scratchpad memories -Hybrid memory system -Architecture -Performance -Efficient -Systems -Memòria ràpida de treball (Informàtica) -Compiladors (Programes d'ordinador) |
Drets:
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Tipus de document:
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Article - Versió presentada Article |
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