Para acceder a los documentos con el texto completo, por favor, siga el siguiente enlace: http://hdl.handle.net/2117/23123
dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
---|---|
dc.contributor | Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors |
dc.contributor.author | Brankovic, Aleksandar |
dc.contributor.author | Stavrou, K. |
dc.contributor.author | Gibert Codina, Enric |
dc.contributor.author | González Colás, Antonio María |
dc.date | 2014 |
dc.identifier.citation | Brankovic, A. [et al.]. Warm-up simulation methodology for HW/SW co-designed processors. A: International Symposium on Code Generation and Optimization. "Proceedings of the 2014 CGO: the twelfth International Symposium on Code Generation and Optimization: February 15-19, 2014: Orlando, Florida". Orlando: ACM, 2014, p. 284-294. |
dc.identifier.citation | 978-1-4503-2670-4 |
dc.identifier.citation | 10.1145/2544137.2544142 |
dc.identifier.uri | http://hdl.handle.net/2117/23123 |
dc.language.iso | eng |
dc.publisher | ACM |
dc.relation | http://dl.acm.org/citation.cfm?id=2544142 |
dc.rights | Attribution-NonCommercial-NoDerivs 3.0 Spain |
dc.rights | info:eu-repo/semantics/openAccess |
dc.rights | http://creativecommons.org/licenses/by-nc-nd/3.0/es/ |
dc.subject | Àrees temàtiques de la UPC::Enginyeria de la telecomunicació::Telemàtica i xarxes d'ordinadors |
dc.subject | Àrees temàtiques de la UPC::Informàtica |
dc.subject | Computer networks |
dc.subject | Fault-tolerant computing |
dc.subject | Dynamic binary translation |
dc.subject | HW/SW co-designed processors |
dc.subject | Simulation |
dc.subject | Warm-up methodology |
dc.subject | Ordinadors, Xarxes d' |
dc.subject | Tolerància als errors (Informàtica) |
dc.title | Warm-up simulation methodology for HW/SW co-designed processors |
dc.type | info:eu-repo/semantics/publishedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
dc.description.abstract | |
dc.description.abstract |