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Hybrid access-specific software cache techniques for the cell BE architecture
O’Brien, Kathryn; O'Brien, Kevin; González Tallada, Marc; Vujic, Nikola; Martorell Bofill, Xavier; Ayguadé Parra, Eduard; Eichenberger, Alexandre E.; Chen, Tong; Sura, Zehra; Zhang, Tao
Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors; Universitat Politècnica de Catalunya. CAP - Grup de Computació d´Altes Prestacions
Ease of programming is one of the main impediments for the broad acceptance of multi-core systems with no hardware support for transparent data transfer between local and global memories. Software cache is a robust approach to provide the user with a transparent view of the memory architecture; but this software approach can suffer from poor performance. In this paper, we propose a hierarchical, hybrid software-cache architecture that classifies at compile time memory accesses in two classes, highlocality and irregular. Our approach then steers the memory references toward one of two specific cache structures optimized for their respective access pattern. The specific cache structures are optimized to enable high-level compiler optimizations to aggressively unroll loops, reorder cache references, and/or transform surrounding loops so as to practically eliminate the software cache overhead in the innermost loop. Performance evaluation indicates that improvements due to the optimized software-cache structures combined with the proposed codeoptimizations translate into 3.5 to 8.4 speedup factors, compared to a traditional software cache approach. As a result, we demonstrate that the Cell BE processor can be a competitive alternative to a modern server-class multi-core such as the IBM Power5 processor for a set of parallel NAS applications.
Peer Reviewed
Àrees temàtiques de la UPC::Informàtica::Enginyeria del software
Cache memory
Compilers (Computer programs)
OpenMP
Compiler optimizations
Local memories
Memory classification
Software cache
Memòria ràpida de treball (Informàtica)
Compiladors (Programes d'ordinador)
info:eu-repo/semantics/publishedVersion
info:eu-repo/semantics/conferenceObject
Association for Computing Machinery
         

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