Título:
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RePP-C: runtime estimation of performance-power with workload consolidation in CMPs
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Autor/a:
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Nishtala, Rajiv; Martorell Bofill, Xavier
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Otros autores:
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Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors; Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
Abstract:
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Configuration of hardware knobs in multicore environments for meeting performance-power demands constitutes a desirable feature in modern data centers. At the same time, high energy efficiency (performance per watt) requires optimal thread-to-core assignment. In this paper, we present the runtime estimator (RePP-C) for performance-power, characterized by processor frequency states (P-states), a wide range of sleep intervals (Cl-states) and workload consolidation. We also present a schema for frequency and contention-aware thread-to-core assignment (FACTS) which considers various thread demands. The proposed solution (RePP-C) selects a given hardware configuration for each active core to ensure that the performance-power demands are satisfied while using the scheduling schema (FACTS) for mapping threads-to-cores. Our results show that FACTS improves over other state-of-the-art schedulers like Distributed Intensity Online (DIO) and native Linux scheduler by 8.25% and 37.56% in performance, with simultaneous improvement in energy efficiency by 6.2% and 14.17%, respectively. Moreover, we prove the usability of RePP-C by predicting performance and power for 7 different types of workloads and 10 different QoS targets. The results show an average error of 7.55% and 8.96% (with 95% confidence interval) when predicting energy and performance respectively. |
Abstract:
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This work has been partially supported by the European Union FP7 program through the Mont-Blanc-2 project (FP7-ICT-610402), by the Ministerio de Economia y Competitividad
under contract Computacion de Altas Prestaciones VII (TIN2015-65316-P), and the Departament d’Innovacio, Universitats i Empresa de la Generalitat de Catalunya, under project MPEXPAR: Models de Programacio i Entorns d’Execucio Paral.lels (2014-SGR-1051). |
Abstract:
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Peer Reviewed |
Materia(s):
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-Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors -Àrees temàtiques de la UPC::Desenvolupament humà i sostenible::Desenvolupament sostenible::Energia i sostenibilitat -High performance computing -Data processing -Sustainability -Quality of service -Instruction sets -Micromechanical devices -Registers -Càlcul intensiu (Informàtica) -Centres informàtics |
Derechos:
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Tipo de documento:
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Artículo - Versión presentada Objeto de conferencia |
Editor:
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Institute of Electrical and Electronics Engineers (IEEE)
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