RTL implementation of a LPDDR4 Memory Controller

Abstract

Memory Controllers play a crucial role in modern systems, being the last stop before accessing memory. DRAM memories require complex access patterns, which make the Controller responsible for orchestrating memory requests and optimizing their access sequences to maximize bandwidth. This project covers the design and implementation of a LPDDR4 Memory Controller. The overall design of the memory controller is described, as well as the rationale behind it. The different architectural and timing constraints, given by the LPDDR4 specification, are also studied, as well as the communication interfaces of the Controller with adjacent modules. Finally, the performance of the controller and various available address mappings is studied, showing how it is able to reach peak bandwidth. Its area and timing characteristics are also analyzed, confirming that it can reach the required operating conditions.