Universitat Politècnica de Catalunya. Doctorat en Arquitectura de Computadors
Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
Barcelona Supercomputing Center
Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
2021-01-01
Current microprocessors include several knobs to modify the hardware behavior in order to improve performance, power, and energy under different workload demands. An impractical and time consuming offline profiling is needed to evaluate the design space to find the optimal knob configuration. Different knobs are typically configured in a decoupled manner to avoid the time-consuming offline profiling process. This can often lead to underperforming configurations and conflicting decisions that jeopardize system power-performance efficiency. Thus, a dynamic management of the different hardware knobs is necessary to find the knob configuration that maximizes system power-performance efficiency without the burden of offline profiling. In this paper, we propose libPRISM, an infrastructure that enables the transparent management of multiple hardware knobs in order to adapt the system to the evolving demands of hardware resources in different workloads. libPRISM can minimize execution time, energy-delay product or power consumption by dynamically managing the SMT level, the data prefetcher, and the DVFS hardware knobs. Overall, the proposed solutions increase performance up to 130% (16.9% on average), reduce energy-delay product up to 80%, and reduce power consumption up to 33% depending on the target metric compared to the default knob configuration of the system.
This work has been supported by the RoMoL ERC Advanced Grant (GA 321253), by the European HiPEAC Network of Excellence, by the Spanish Ministry of Science and Innovation (contracts TIN2015-65316-P), by Generalitat de Catalunya (contracts 2014-SGR-1051 and 2014-SGR-1272) and by IBM/BSC Deep Learning Center initiative.This research was developed in part with funding from the Defense Advanced Research Projects Agency (DARPA).
Peer Reviewed
Postprint (author's final draft)
Article
English
Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors; Parallel programming (Computer science); Microprocessors; High performance computing; HPC; Parallel programming; Runtime; SMT; Data prefetcher; DVFS; Programació en paral·lel (Informàtica); Microprocessadors
Institute of Electrical and Electronics Engineers (IEEE)
https://ieeexplore-ieee-org.recursos.biblioteca.upc.edu/document/9035455/
info:eu-repo/grantAgreement/MINECO//TIN2015-65316-P/ES/COMPUTACION DE ALTAS PRESTACIONES VII/
info:eu-repo/grantAgreement/AGAUR/V PRI/2014 SGR 1051
info:eu-repo/grantAgreement/AGAUR/V PRI/2014 SGR 1272
info:eu-repo/grantAgreement/EC/FP7/321253/EU/Riding on Moore's Law/ROMOL
info:eu-repo/grantAgreement/MINECO/1PE/2016-30984
Open Access
E-prints [73026]