Universitat Politècnica de Catalunya
Universitat Politècnica de Catalunya. Departament de Ciències de la Computació
Universitat Politècnica de Catalunya. ALBCOM - Algorismia, Bioinformàtica, Complexitat i Mètodes Formals
2006
We formally define - at the stream transformer level - a class of synchronous circuits that tolerate any variability in the latency of their environment. We study behavioral properties of networks of such circuits and prove fundamental compositionality results. The paper contributes to bridging the gap between the theory of latency-insensitive systems and the correct implementation of efficient control structures for them.
Peer Reviewed
Postprint (published version)
Conference report
English
Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats; Logic circuits; Circuits; Adders; Delay; Timing; Wires; Process design; Design methodology; Control systems; Communications technology; Microarchitecture; Circuits lògics
Institute of Electrical and Electronics Engineers (IEEE)
https://ieeexplore.ieee.org/document/4021004
Open Access
E-prints [73020]
