Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
1988
The authors consider the description of a systolic algorithm to solve the connected-component problem. It is executed in a ring topology with N processors, requiring O(Nlog N) time without regard to the graph's sparsity. The algorithm-partitioning issue is also addressed, indicating how to optimally map the computations into fixed-size rings or linear arrays. The proposed algorithm leads to simple processing elements, data addressing, and control. These points make the systolic array highly implementable.
Peer Reviewed
Postprint (published version)
Conference report
English
Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors; Parallel algorithms; Multiprocessors; Cellular arrays; Computer architecture; Multiprocessing systems; Algorismes paral·lels; Multiprocessadors
Institute of Electrical and Electronics Engineers (IEEE)
http://ieeexplore.ieee.org/document/15396/
Open Access
E-prints [73034]