dc.contributor
Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.contributor
Canal Corretger, Ramon
dc.contributor.author
Zhuang, Sicong
dc.date.issued
2014-09-09
dc.identifier
https://hdl.handle.net/2099.1/22656
dc.description.abstract
This thesis exploits a multi-band cache-like register file architecture to mitigate the potential damage caused by process variations and soft error (single event upsets). An quantitative analysis is conducted to measure the possible gains and loses by incorporating it using simulation results.
dc.format
application/pdf
dc.publisher
Universitat Politècnica de Catalunya
dc.subject
Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject
Microprocessors
dc.subject
process variation
dc.subject
process variation
dc.subject
Microprocessadors
dc.title
Improving The Robustness Of The Register File: a Register File Cache Architecture
