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dc.contributor | Universitat Politècnica de Catalunya. Doctorat en Enginyeria Electrònica |
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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica |
dc.contributor | Universitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions |
dc.contributor.author | Escudero López, Manuel |
dc.contributor.author | Vourkas, Ioannis |
dc.contributor.author | Rubio Sola, Jose Antonio |
dc.contributor.author | Moll Echeto, Francisco de Borja |
dc.date | 2019-01-01 |
dc.identifier.citation | Escudero, M. [et al.]. Memristive logic in crossbar memory arrays: Variability-aware design for higher reliability. "IEEE transactions on nanotechnology", 1 Gener 2019, vol. 18, p. 635-646. |
dc.identifier.citation | 1536-125X |
dc.identifier.citation | 10.1109/TNANO.2019.2923731 |
dc.identifier.uri | http://hdl.handle.net/2117/168773 |
dc.language.iso | eng |
dc.relation | https://ieeexplore.ieee.org/document/8745694 |
dc.relation | info:eu-repo/grantAgreement/ES/1PE/TEC2016-75151-C3-2-R |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats |
dc.subject | Àrees temàtiques de la UPC::Enginyeria electrònica::Components electrònics::Transistors |
dc.subject | Integrated circuits |
dc.subject | Transistors |
dc.subject | Memristor |
dc.subject | MAGIC |
dc.subject | CNIMP |
dc.subject | IMPLY |
dc.subject | Ratioed logic |
dc.subject | In-memory computing |
dc.subject | Resistive switching |
dc.subject | Crossbar array |
dc.subject | Circuits integrats |
dc.subject | Transistors |
dc.title | Memristive logic in crossbar memory arrays: Variability-aware design for higher reliability |
dc.type | info:eu-repo/semantics/submittedVersion |
dc.type | info:eu-repo/semantics/article |
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