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dc.contributor | Universitat Politècnica de Catalunya. Departament de Ciències de la Computació |
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dc.contributor | Universitat Politècnica de Catalunya. ALBCOM - Algorismia, Bioinformàtica, Complexitat i Mètodes Formals |
dc.contributor.author | Moreno Vega, Alberto |
dc.contributor.author | Cortadella, Jordi |
dc.date | 2018 |
dc.identifier.citation | Moreno, A.; Cortadella, J. State encoding of asynchronous controllers using pseudo-boolean optimization. A: IEEE International Symposium on Asynchronous Circuits and Systems. "2018 24th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2018: Vienna, Austria, 13-16 May 2018: proceedings". Institute of Electrical and Electronics Engineers (IEEE), 2018, p. 9-16. |
dc.identifier.citation | 978-1-5386-5883-3 |
dc.identifier.citation | 10.1109/ASYNC.2018.00013 |
dc.identifier.uri | http://hdl.handle.net/2117/132479 |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.relation | https://ieeexplore.ieee.org/document/8589536 |
dc.relation | info:eu-repo/grantAgreement/AEI/TIN2017-86727-C2-1-R |
dc.relation | info:eu-repo/grantAgreement/AGAUR/2017 SGR 786 |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats |
dc.subject | Asynchronous circuits |
dc.subject | Computational complexity |
dc.subject | Asynchronous controllers |
dc.subject | State encoding |
dc.subject | SAT |
dc.subject | Pseudo boolean minimization |
dc.subject | Circuits asíncrons |
dc.subject | Complexitat computacional |
dc.title | State encoding of asynchronous controllers using pseudo-boolean optimization |
dc.type | info:eu-repo/semantics/submittedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
dc.description.abstract | |
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