|
Title:
|
Synthesis of asynchronous control circuits with automatically generated relative timing assumptions
|
|
Author:
|
Cortadella, Jordi; Kishinevsky, Michael; Burns, Steven M.; Stevens, Kenneth S.
|
|
Other authors:
|
Universitat Politècnica de Catalunya. Departament de Ciències de la Computació; Universitat Politècnica de Catalunya. ALBCOM - Algorismia, Bioinformàtica, Complexitat i Mètodes Formals |
|
Abstract:
|
This paper describes a method of synthesis of asynchronous circuits with relative timing. Asynchronous communication between gates and modules typically utilizes handshakes to ensure functionality. Relative timing assumptions in the form "event a occurs before event b" can be used to remove redundant handshakes and associated logic. This paper presents a method for automatic generation of relative timing assumptions from the untimed specification. These assumptions can be used for area and delay optimization of the circuit. A set of relative timing constraints sufficient for the correct operation of the circuit is back-annotated to the designer. Experimental results for control circuits of a prototype iA32 instruction length decoding and steering unit called RAPPID (Revolving Asynchronous Pentium(R)Processor Instruction Decoder) shows significant improvements in area and delay over speed-independent circuits. |
|
Abstract:
|
Peer Reviewed |
|
Subject(s):
|
-Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats
-Asynchronous circuits
-Logic design
-Circuit synthesis
-Automatic control
-Timing
-Delay
-Decoding
-Communication system control
-Asynchronous communication
-Logic
-Prototypes
-Circuits asíncrons
-Estructura lògica |
|
Rights:
|
|
|
Document type:
|
Article - Published version
Conference Object |
|
Published by:
|
Institute of Electrical and Electronics Engineers (IEEE)
|
|
Share:
|
|
