Synthesis of speed-independent circuits from STG-unfolding segment

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To access the full text documents, please follow this link: http://hdl.handle.net/2117/130227

dc.contributor	Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.contributor	Universitat Politècnica de Catalunya. Departament de Ciències de la Computació
dc.contributor	Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.contributor	Universitat Politècnica de Catalunya. ALBCOM - Algorismia, Bioinformàtica, Complexitat i Mètodes Formals
dc.contributor.author	Semenov, Alex
dc.contributor.author	Yakovlev, Alex
dc.contributor.author	Pastor Llorens, Enric
dc.contributor.author	Peña Basurto, Marco Antonio
dc.contributor.author	Cortadella, Jordi
dc.date	1997
dc.identifier.citation	Semenov, A. [et al.]. Synthesis of speed-independent circuits from STG-unfolding segment. A: Design Automation Conference. "Design Automation Conference, 34th DAC: Anaheim, CA, Anaheim Convention Center, June 9-13,1997: proceedings 1997". Institute of Electrical and Electronics Engineers (IEEE), 1997, p. 16-21.
dc.identifier.citation	0-7803-4093-0
dc.identifier.citation	10.1109/DAC.1997.597110
dc.identifier.uri	http://hdl.handle.net/2117/130227
dc.language.iso	eng
dc.publisher	Institute of Electrical and Electronics Engineers (IEEE)
dc.relation	https://ieeexplore.ieee.org/document/597110
dc.rights	info:eu-repo/semantics/openAccess
dc.subject	Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats
dc.subject	Logic design
dc.subject	Logic circuits
dc.subject	Circuit synthesis
dc.subject	Signal synthesis
dc.subject	Permission
dc.subject	Data structures
dc.subject	Boolean functions
dc.subject	Concurrent computing
dc.subject	Logic
dc.subject	Explosions
dc.subject	Samarium
dc.subject	Collaborative work
dc.subject	Estructura lògica
dc.subject	Circuits lògics
dc.title	Synthesis of speed-independent circuits from STG-unfolding segment
dc.type	info:eu-repo/semantics/publishedVersion
dc.type	info:eu-repo/semantics/conferenceObject
dc.description.abstract	This paper presents a novel technique for synthesis of speed-independent circuits. It is based on partial order representation of the state graph called STG-unfolding segment. The new method uses approximation technique to speed up the synthesis process. The method is illustrated on the basic implementation architecture. Experimental results demonstrating its efficiency are presented and discussed.
dc.description.abstract	Peer Reviewed

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