To access the full text documents, please follow this link: http://hdl.handle.net/2117/130146
dc.contributor | Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica |
---|---|
dc.contributor | Universitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions |
dc.contributor.author | Escudero López, Manuel |
dc.contributor.author | Rubio Sola, Jose Antonio |
dc.contributor.author | Moll Echeto, Francisco de Borja |
dc.contributor.author | Vourkas, Ioannis |
dc.date | 2018 |
dc.identifier.citation | Escudero, M. [et al.]. Variability-tolerant memristor-based ratioed logic in crossbar array. A: IEEE/ACM International Symposium on Nanoscale Architectures. "2018 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 2018): Athens, Greece: 17-19 July 2018". Institute of Electrical and Electronics Engineers (IEEE), 2018, p. 1-6. |
dc.identifier.citation | 9781538662939 |
dc.identifier.citation | 10.1145/3232195.3232213 |
dc.identifier.uri | http://hdl.handle.net/2117/130146 |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.relation | https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8604365 |
dc.relation | info:eu-repo/grantAgreement/ES/1PE/TEC2016-75151-C3-2-R |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject | Àrees temàtiques de la UPC::Enginyeria elèctrica |
dc.subject | Computer architecture |
dc.subject | Ratioed logic gates |
dc.subject | crossbar |
dc.subject | memristor |
dc.subject | logic design |
dc.subject | variability- aware design. |
dc.subject | Arquitectura d'ordinadors |
dc.title | Variability-tolerant memristor-based ratioed logic in crossbar array |
dc.type | info:eu-repo/semantics/submittedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
dc.description.abstract | |
dc.description.abstract | |
dc.description.abstract |