The Wireless Network-on-Chip paradigm offers important advantages in the area of many-core processors: boardband communications, reconfigurable network topologies and flexibility. Further information about this paradigm can be found in: http://www.n3cat.upc.edu/papers/Evaluating_the_Feasibility_of_Wireless_Networks-on-Chip_Enabled_by_Graphene.pdf

This project involves a study of neural networks execution on different hardware architectures where they can be processed in, i.e. CPUs, GPUs and specialized AI accelerators. FPGAs are left out from this study. Different tests will be performed on the architectures, demonstrating its capacity, specially in terms of parallelization. The study includes a previous detailed DNN mathematical description to help the understanding of the underlying computation the hardware is performing. Finally, they are also evaluated on the feasibility of incorporating a Wireless Network on Chip (WNoC, intra-processor wireless communication) to the different processors to improve their global performance.