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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
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dc.contributor | Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors |
dc.contributor.author | Parcerisa Bundó, Joan Manuel |
dc.contributor.author | Sahuquillo, Julio |
dc.contributor.author | González Colás, Antonio María |
dc.contributor.author | Duato, José |
dc.date | 2002 |
dc.identifier.citation | Parcerisa, J.M., Sahuquillo, J., González, A., Duato, J. Efficient interconnects for clustered microarchitectures. A: International Conference on Parallel Architectues and Compilation Techniques. "2002 International Conference on Parallel Architectures and Compilation Techniques, PACT 2002: 22-25 September 2002, Charlottesville, Virginia, USA: proceedings". Charlottesville, Virginia: Institute of Electrical and Electronics Engineers (IEEE), 2002, p. 291-300. |
dc.identifier.citation | 0-7695-1620-3 |
dc.identifier.citation | 10.1109/PACT.2002.1106028 |
dc.identifier.uri | http://hdl.handle.net/2117/100592 |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.relation | http://ieeexplore.ieee.org/abstract/document/1106028/ |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject | Parallel processing (Electronic computers) |
dc.subject | Microarchitecture |
dc.subject | Registers |
dc.subject | Multiprocessor interconnection networks |
dc.subject | Logic |
dc.subject | Delay |
dc.subject | Network topology |
dc.subject | Hardware |
dc.subject | Processament en paral·lel (Ordinadors) |
dc.title | Efficient interconnects for clustered microarchitectures |
dc.type | info:eu-repo/semantics/publishedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
dc.description.abstract | |
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