Through-silicon vias (TSVs) are critical elements in 3-D integrated circuits susceptible to defects during fabrication and lifetime. It is desirable to detect defective TSVs in the early steps of the fabrication process to prevent stacking yield loss. Thus, the development of effective prebond testing techniques becomes of great importance. In this direction, recent research effort has been devoted to the development of two main prebond techniques: 1) prebond probing and 2) built-in self-test (BIST) techniques. The prebond probing poses economic and technological challenges, whereas current BIST proposals have disadvantages for certain solutions. Hence, there is still a need for an effective methodology in terms of fault coverage, area overhead, and test time. This paper proposes a BIST technique based on a simple unbalanced circuit comparing the behavior of two TSVs. Electrical simulation results show the viability of the proposal to detect weak defects, i.e., resistive opens and resistive bridges, adding reasonable area overhead in a short-test application time. Furthermore, an experimental design is built on a 65-nm technology, where resistive open defects are intentionally injected. Automated test equipment measurements confirm the simulation results