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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
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dc.contributor | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.contributor.author | Álvarez Martí, Lluc |
dc.contributor.author | Casas, Marc |
dc.contributor.author | Labarta Mancho, Jesús José |
dc.contributor.author | Ayguadé Parra, Eduard |
dc.contributor.author | Valero Cortés, Mateo |
dc.contributor.author | Moreto Planas, Miquel |
dc.date | 2018 |
dc.identifier.citation | Álvarez, L., Casas, M., Labarta, J., Ayguadé, E., Valero, M., Moreto, M. Runtime-guided management of stacked DRAM memories in task parallel programs. A: International Conference on Supercomputing. "Proceedings of the 2018 International Conference on Supercomputing: Beijing, China, June 12-15, 2018". New York: Association for Computing Machinery (ACM), 2018, p. 218-228. |
dc.identifier.citation | 978-1-4503-5783-8 |
dc.identifier.citation | 10.1145/3205289.3205312 |
dc.identifier.uri | http://hdl.handle.net/2117/125344 |
dc.language.iso | eng |
dc.publisher | Association for Computing Machinery (ACM) |
dc.relation | https://dl.acm.org/citation.cfm?id=3205312 |
dc.relation | info:eu-repo/grantAgreement/AGAUR/V PRI/2014 SGR 1272 |
dc.relation | info:eu-repo/grantAgreement/AGAUR/V PRI/2014 SGR 1051 |
dc.relation | info:eu-repo/grantAgreement/ES/1PE/TIN2015-65316-P |
dc.relation | info:eu-repo/grantAgreement/AEI/RYC-2016-21104 |
dc.relation | info:eu-repo/grantAgreement/EC/H2020/321253 |
dc.relation | info:eu-repo/grantAgreement/EC/H2020/779877 |
dc.relation | info:eu-repo/grantAgreement/ES/PE2013-2016/TIN2015-65316-P |
dc.relation | info:eu-repo/grantAgreement/ES/PE2013-2016/RYC-2016-21104 |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject | High performance computing |
dc.subject | Memory management (Computer science) |
dc.subject | Runtime systems |
dc.subject | Stacked DRAM memories |
dc.subject | Task-based data-flow programming models |
dc.subject | Data flow analysis |
dc.subject | Hardware |
dc.subject | Intelligent control |
dc.subject | Memory architecture |
dc.subject | Application codes |
dc.subject | Complex hardware |
dc.subject | Dataflow programming |
dc.subject | Dram memory |
dc.subject | HPC |
dc.subject | Runtime approach |
dc.subject | Task-based programming |
dc.subject | Dynamic random access storage |
dc.subject | Càlcul intensiu (Informàtica) |
dc.subject | Gestió de memòria (Informàtica) |
dc.title | Runtime-guided management of stacked DRAM memories in task parallel programs |
dc.type | info:eu-repo/semantics/submittedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
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