Para acceder a los documentos con el texto completo, por favor, siga el siguiente enlace: http://hdl.handle.net/2117/113578
dc.contributor | Universitat Politècnica de Catalunya. Departament d'Enginyeria de Sistemes, Automàtica i Informàtica Industrial |
---|---|
dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
dc.contributor | Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica |
dc.contributor | Universitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions |
dc.contributor | Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors |
dc.contributor.author | Amat, Esteve |
dc.contributor.author | Calomarde Palomino, Antonio |
dc.contributor.author | Canal Corretger, Ramon |
dc.contributor.author | Rubio Sola, Jose Antonio |
dc.date | 2017 |
dc.identifier.citation | Amat, E., Calomarde, A., Canal, R., Rubio, A. Suitability of FinFET introduction into eDRAM cells for operate at sub-threshold level. A: International Workshop on Power and Timing Modeling, Optimization and Simulation. "27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS 2017): Thessaloniki, Greece, Sept. 25-27, 2017". Thessaloniki: Institute of Electrical and Electronics Engineers (IEEE), 2017, p. 1-6. |
dc.identifier.citation | 9781509064618 |
dc.identifier.citation | 10.1109/PATMOS.2017.8106951 |
dc.identifier.uri | http://hdl.handle.net/2117/113578 |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.relation | http://ieeexplore.ieee.org/document/8106951/ |
dc.rights | Attribution-NonCommercial-NoDerivs 3.0 Spain |
dc.rights | info:eu-repo/semantics/openAccess |
dc.rights | http://creativecommons.org/licenses/by-nc-nd/3.0/es/ |
dc.subject | Àrees temàtiques de la UPC::Enginyeria electrònica |
dc.subject | Electronics |
dc.subject | FinFET |
dc.subject | eDRAM |
dc.subject | sub-VT |
dc.subject | single event upsets |
dc.subject | variability |
dc.subject | reliability. |
dc.subject | Enginyeria electrònica |
dc.title | Suitability of FinFET introduction into eDRAM cells for operate at sub-threshold level |
dc.type | info:eu-repo/semantics/submittedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
dc.description.abstract | |
dc.description.abstract |