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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
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dc.contributor | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.contributor.author | Moreto Planas, Miquel |
dc.contributor.author | Cazorla Almeida, Francisco Javier |
dc.contributor.author | Ramírez Bellido, Alejandro |
dc.contributor.author | Valero Cortés, Mateo |
dc.date | 2007 |
dc.identifier.citation | Moreto, M., Cazorla, F., Ramirez, A., Valero, M. MLP-aware dynamic cache partitioning. A: International Conference on Parallel Architectures and Compilation Techniques. "16th International Conference on Parallel Architecture and Compilation Techniques, PACT 2007: 15-19 September 2007, Brasov, Romania". Brasov: Institute of Electrical and Electronics Engineers (IEEE), 2007, p. 418. |
dc.identifier.citation | 978-0-7695-2944-8 |
dc.identifier.citation | 10.1109/PACT.2007.4336246 |
dc.identifier.uri | http://hdl.handle.net/2117/113041 |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.relation | http://ieeexplore.ieee.org/document/4336246/ |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject | Cache memory |
dc.subject | Multiprocessors |
dc.subject | Resource allocation |
dc.subject | Cache storage |
dc.subject | Multiprocessing systems |
dc.subject | Multi-threading |
dc.subject | Memòria ràpida de treball (Informàtica) |
dc.subject | Multiprocessadors |
dc.title | MLP-aware dynamic cache partitioning |
dc.type | info:eu-repo/semantics/publishedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
dc.description.abstract | |
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