Per accedir als documents amb el text complet, si us plau, seguiu el següent enllaç: http://hdl.handle.net/2117/113050
dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
---|---|
dc.contributor | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.contributor.author | Ramírez Bellido, Alejandro |
dc.contributor.author | Larriba Pey, Josep |
dc.contributor.author | Navarro García, Carlos |
dc.contributor.author | Serrano, Xavier |
dc.contributor.author | Valero Cortés, Mateo |
dc.contributor.author | Torrellas, Josep |
dc.date | 1999 |
dc.identifier.citation | Ramírez, A., Larriba, J., Navarro, C., Serrano, X., Valero, M., Torrellas, J. Optimization of instruction fetch for decision support workloads. A: International Conference on Parallel Processing. "1999 InternationaI Conference on Parallel Processing: 21-24 September 1999, Aizu-Wakamatsu City, Japan: proceedings". Aizu-Wakamatsu: Institute of Electrical and Electronics Engineers (IEEE), 1999, p. 238-245. |
dc.identifier.citation | 0-7695-0350-0 |
dc.identifier.citation | 10.1109/ICPP.1999.797409 |
dc.identifier.uri | http://hdl.handle.net/2117/113050 |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.relation | http://ieeexplore.ieee.org/document/797409/ |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject | Parallel processing (Electronic computers) |
dc.subject | Database design |
dc.subject | Performance evaluation |
dc.subject | Processament en paral·lel (Ordinadors) |
dc.subject | Bases de dades -- Disseny |
dc.title | Optimization of instruction fetch for decision support workloads |
dc.type | info:eu-repo/semantics/publishedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
dc.description.abstract | |
dc.description.abstract |