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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
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dc.contributor | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.contributor.author | Pericàs Gleim, Miquel |
dc.contributor.author | Cristal Kestelman, Adrián |
dc.contributor.author | González García, Rubén |
dc.contributor.author | Jiménez, Daniel A. |
dc.contributor.author | Valero Cortés, Mateo |
dc.date | 2006 |
dc.identifier.citation | Pericàs, M., Cristal, A., González, R., Jiménez, D. A., Valero, M. A decoupled KILO-instruction processor. A: International Symposium on High-Performance Computer Architecture. "The Twelfth International Symposium on High-Performance Computer Architecture, 2006". Texas: Institute of Electrical and Electronics Engineers (IEEE), 2006, p. 52-63. |
dc.identifier.citation | 0-7803-9368-6 |
dc.identifier.citation | 10.1109/HPCA.2006.1598112 |
dc.identifier.uri | http://hdl.handle.net/2117/112374 |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.relation | http://ieeexplore.ieee.org/document/1598112/ |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject | Microprocessors |
dc.subject | Cache memory |
dc.subject | Multiprocessing systems |
dc.subject | Instruction sets |
dc.subject | Computer architecture |
dc.subject | Cache storage |
dc.subject | Microprocessadors |
dc.subject | Memòria ràpida de treball (Informàtica) |
dc.title | A decoupled KILO-instruction processor |
dc.type | info:eu-repo/semantics/publishedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
dc.description.abstract | |
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