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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
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dc.contributor | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.contributor.author | Santana Jaria, Oliverio J. |
dc.contributor.author | Ramírez Bellido, Alejandro |
dc.contributor.author | Valero Cortés, Mateo |
dc.date | 2004 |
dc.identifier.citation | Santana, O., Ramírez, A., Valero, M. Reducing fetch architecture complexity using procedure inlining. A: Workshop on Interaction between Compilers and Computer Architecture. "INTERACT-8 2004: Eighth Workshop on Interaction between Compilers and Computer Architectures". Madrid: Institute of Electrical and Electronics Engineers (IEEE), 2004, p. 97-106. |
dc.identifier.citation | 0-7695-2061-8 |
dc.identifier.citation | 10.1109/INTERA.2004.1299514 |
dc.identifier.uri | http://hdl.handle.net/2117/112123 |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.relation | http://ieeexplore.ieee.org/document/1299514/ |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject | Compilers (Computer programs) |
dc.subject | Computer storage devices |
dc.subject | Parallel processing (Electronic computers) |
dc.subject | Memory architecture |
dc.subject | Program compilers |
dc.subject | Storage management |
dc.subject | Cache storage |
dc.subject | Instruction sets |
dc.subject | Compiladors (Programes d'ordinador) |
dc.subject | Ordinadors -- Memòries |
dc.subject | Processament en paral·lel (Ordinadors) |
dc.title | Reducing fetch architecture complexity using procedure inlining |
dc.type | info:eu-repo/semantics/publishedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
dc.description.abstract | |
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