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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
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dc.contributor | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.contributor.author | Espasa Sans, Roger |
dc.contributor.author | Valero Cortés, Mateo |
dc.date | 1996 |
dc.identifier.citation | Espasa, R., Valero, M. Decoupled vector architectures. A: International Symposium on High-Performance Computer Architecture. "Second International Symposium on High-Performance Computer Architecture: February 3-7, 1996, San Jose, California: proceedings". San Jose, California: Institute of Electrical and Electronics Engineers (IEEE), 1996, p. 281-290. |
dc.identifier.citation | 0-8186-7237-4 |
dc.identifier.citation | 10.1109/HPCA.1996.501193 |
dc.identifier.uri | http://hdl.handle.net/2117/112019 |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.relation | http://ieeexplore.ieee.org/document/501193/ |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject | Telecommunication -- Traffic -- Management |
dc.subject | Parallel processing (Electronic computers) |
dc.subject | Delay |
dc.subject | Parallel processing |
dc.subject | Yarn |
dc.subject | Hardware |
dc.subject | Computer aided instruction |
dc.subject | Computer architecture |
dc.subject | Vector processors |
dc.subject | Computational modeling |
dc.subject | Costs |
dc.subject | Multithreading |
dc.subject | Telecomunicació -- Tràfic -- Gestió |
dc.subject | Processament en paral·lel (Ordinadors) |
dc.title | Decoupled vector architectures |
dc.type | info:eu-repo/semantics/publishedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
dc.description.abstract | |
dc.description.abstract |