Para acceder a los documentos con el texto completo, por favor, siga el siguiente enlace: http://hdl.handle.net/2117/105885
dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
---|---|
dc.contributor | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.contributor.author | Cazorla, Francisco |
dc.contributor.author | Knijnenburg, Peter M.W. |
dc.contributor.author | Sakellariou, Rizos |
dc.contributor.author | Fernandez Prieto, Enrique |
dc.contributor.author | Ramírez Bellido, Alejandro |
dc.contributor.author | Valero Cortés, Mateo |
dc.date | 2006-07 |
dc.identifier.citation | Cazorla, F., Knijnenburg, P., Sakellariou, R., Fernández, E., Ramírez, A., Valero, M. Predictable performance in SMT processors: synergy between the OS and SMTs. "IEEE transactions on computers", Juliol 2006, vol. 55, núm. 7, p. 785-799. |
dc.identifier.citation | 0018-9340 |
dc.identifier.citation | 10.1109/TC.2006.108 |
dc.identifier.uri | http://hdl.handle.net/2117/105885 |
dc.language.iso | eng |
dc.relation | http://ieeexplore.ieee.org/document/1637396/ |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject | Operating systems (Computers) |
dc.subject | Simultaneous multithreading processors |
dc.subject | Embedded computer systems |
dc.subject | Multithreaded processors |
dc.subject | Simultaneous multithreading |
dc.subject | ILP |
dc.subject | Thread-level parallelism |
dc.subject | Performance predictability |
dc.subject | Real time |
dc.subject | Operating systems |
dc.subject | Sistemes operatius (Ordinadors) |
dc.subject | Ordinadors immersos, Sistemes d' |
dc.title | Predictable performance in SMT processors: synergy between the OS and SMTs |
dc.type | info:eu-repo/semantics/publishedVersion |
dc.type | info:eu-repo/semantics/article |
dc.description.abstract | |
dc.description.abstract |