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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
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dc.contributor | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.contributor.author | Benedicte Illescas, Pedro |
dc.contributor.author | Kosmidis, Leonidas |
dc.contributor.author | Quiñones, Eduardo |
dc.contributor.author | Abella Ferrer, Jaume |
dc.contributor.author | Cazorla Almeida, Francisco Javier |
dc.date | 2016 |
dc.identifier.citation | Benedicte, P., Kosmidis, L., Quiñones, E., Abella, J., Cazorla, F. Modelling the confidence of timing analysis for time randomised caches. A: IEEE International Symposium on Industrial Embedded Systems. "2016 11th IEEE International Symposium on Industrial Embedded Systems (SIES): Krakow, Poland 23-25 May 2016: proceedings". Krakow: Institute of Electrical and Electronics Engineers (IEEE), 2016, p. 1-8. |
dc.identifier.citation | 978-1-5090-2282-3 |
dc.identifier.citation | 10.1109/SIES.2016.7509421 |
dc.identifier.uri | http://hdl.handle.net/2117/96651 |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.relation | http://ieeexplore.ieee.org/document/7509421/ |
dc.relation | info:eu-repo/grantAgreement/ES/1PE/TIN2015-65316-P |
dc.relation | info:eu-repo/grantAgreement/ES/RYC-2013-14717 |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject | Cache memory |
dc.subject | Embedded computer systems |
dc.subject | Timing |
dc.subject | Reliability |
dc.subject | Hardware |
dc.subject | Standards |
dc.subject | Safety |
dc.subject | Probabilistic logic |
dc.subject | Memòria ràpida de treball (Informàtica) |
dc.subject | Ordinadors immersos, Sistemes d' |
dc.title | Modelling the confidence of timing analysis for time randomised caches |
dc.type | info:eu-repo/semantics/submittedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
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