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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
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dc.contributor | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.contributor.author | Castillo, Emilio |
dc.contributor.author | Moreto Planas, Miquel |
dc.contributor.author | Casas, Marc |
dc.contributor.author | Álvarez Martí, Lluc |
dc.contributor.author | Vallejo, Enrique |
dc.contributor.author | Chronaki, Kallia |
dc.contributor.author | Badia Sala, Rosa Maria |
dc.contributor.author | Bosque Orero, José Luis |
dc.contributor.author | Beivide Palacio, Julio Ramón |
dc.contributor.author | Ayguadé Parra, Eduard |
dc.contributor.author | Labarta Mancho, Jesús José |
dc.contributor.author | Valero Cortés, Mateo |
dc.date | 2016 |
dc.identifier.citation | Castillo, E., Moreto, M., Casas, M., Álvarez, Ll., Vallejo, E., Chronaki, K., Badia, R.M., Bosque, J., Beivide, R., Ayguadé, E., Labarta, J., Valero, M. CATA: Criticality aware task acceleration for multicore processors. A: IEEE International Parallel and Distributed Processing Symposium. "IPDPS 2016: 2016 IEEE 30th International Parallel and Distributed Processing Symposium: proceedings". Chicago, Illinois: Institute of Electrical and Electronics Engineers (IEEE), 2016, p. 413-422. |
dc.identifier.citation | 978-1-5090-2140-6 |
dc.identifier.citation | 10.1109/IPDPS.2016.49 |
dc.identifier.uri | http://hdl.handle.net/2117/90643 |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.relation | http://ieeexplore.ieee.org/document/7516037/ |
dc.relation | info:eu-repo/grantAgreement/ES/6PN/TIN2012-34557 |
dc.relation | info:eu-repo/grantAgreement/ES/1PE/TIN2015-65316-P |
dc.relation | info:eu-repo/grantAgreement/ES/1PE/TIN2013-46957-C2-1-P |
dc.relation | info:eu-repo/grantAgreement/EC/FP7/321253/EU/Riding on Moore's Law/ROMOL |
dc.relation | info:eu-repo/grantAgreement/EC/H2020/671697/EU/Mont-Blanc 3, European scalable and power efficient HPC platformbased on low-power embedded technology/Mont-Blanc 3 |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject | Multiprocessors |
dc.subject | Runtime |
dc.subject | Hardware |
dc.subject | Acceleration |
dc.subject | Programming |
dc.subject | Program processors |
dc.subject | Multicore processing |
dc.subject | Cats |
dc.subject | Scheduling |
dc.subject | Multiprocessing systems |
dc.subject | Multiprocessadors |
dc.title | CATA: Criticality aware task acceleration for multicore processors |
dc.type | info:eu-repo/semantics/submittedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
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