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Title:
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Modulo scheduling for a fully-distributed clustered VLIW architecture
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Author:
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Sánchez Navarro, F. Jesús; González Colás, Antonio María
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Other authors:
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Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors; Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors |
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Abstract:
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Clustering is an approach that many microprocessors are adopting in recent times in order to mitigate the increasing penalties of wire delays. We propose a novel clustered VLIW architecture which has all its resources partitioned among clusters, including the cache memory. A modulo scheduling scheme for this architecture is also proposed. This algorithm takes into account both register and memory inter-cluster communications so that the final schedule results in a cluster assignment that favors cluster locality in cache references and register accesses. It has been evaluated for both 2- and 4-cluster configurations and for differing numbers and latencies of inter-cluster buses. The proposed algorithm produces schedules with very low communication requirements and outperforms previous cluster-oriented schedulers. |
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Abstract:
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Peer Reviewed |
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Subject(s):
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-Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
-Parallel processing (Electronic computers)
-Cache memory
-Microprocessors
-VLIW
-Processor scheduling
-Delay
-Clustering algorithms
-Scheduling algorithm
-Registers
-Wire
-Cache memory
-Partitioning algorithms
-Processament en paral·lel (Ordinadors)
-Memòria ràpida de treball (Informàtica)
-Microprocessadors |
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Rights:
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Document type:
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Article - Published version
Conference Object |
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Published by:
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Institute of Electrical and Electronics Engineers (IEEE)
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