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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
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dc.contributor | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.contributor.author | Jiménez, Víctor |
dc.contributor.author | Buyuktosunoglu, Alper |
dc.contributor.author | Bose, Pradip |
dc.contributor.author | O'Connell, Francis P. |
dc.contributor.author | Cazorla Almeida, Francisco Javier |
dc.contributor.author | Valero Cortés, Mateo |
dc.date | 2015 |
dc.identifier.citation | Jiménez, V., Buyuktosunoglu, A., Bose, P., O'Connell, F., Cazorla, F., Valero, M. Increasing multicore system efficiency through intelligent bandwidth shifting. A: International Symposium on High-Performance Computer Architecture. "2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA 2015): Burlingame, California, USA: 7-11 February 2015". San Francisco Bay Area, California: Institute of Electrical and Electronics Engineers (IEEE), 2015, p. 39-50. |
dc.identifier.citation | 978-1-4799-8931-7 |
dc.identifier.citation | 10.1109/HPCA.2015.7056020 |
dc.identifier.uri | http://hdl.handle.net/2117/84776 |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.relation | http://ieeexplore.ieee.org/xpl/articleDetails.jsp?reload=true&arnumber=7056020 |
dc.relation | info:eu-repo/grantAgreement/EC/FP7/321253/EU/Riding on Moore's Law/ROMOL |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject | Memory management (Computer science) |
dc.subject | Microprocessor chips |
dc.subject | Multiprocessing systems |
dc.subject | Storage management |
dc.subject | Gestió de memòria (Informàtica) |
dc.title | Increasing multicore system efficiency through intelligent bandwidth shifting |
dc.type | info:eu-repo/semantics/publishedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
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