A wide range of attacks that target cache memories in secure systems have been reported in the last half decade. Cold-boot attacks can be thwarted through the recently proposed Interleaved Scrambling Technique (IST). However, side channel attacks like the Simple Power Analysis (SPA) can still circumvent this protection. Error detection and correction codes (EDC/ECC) are employed in memories to increase reliability, but they can also be used to increase the security. This paper proposes to boost the IST with an ECC code in order to create a cache resistant against SPA-attacks. The redundancy provided by the ECC code is used to create confusion by enlarging the search space where the hacker has to look for to find the secret keys.