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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica |
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dc.contributor | Universitat Politècnica de Catalunya. QINE - Disseny de Baix Consum, Test, Verificació i Circuits Integrats de Seguretat |
dc.contributor.author | Rodríguez Montañés, Rosa |
dc.contributor.author | Arumi Delgado, Daniel |
dc.contributor.author | Figueras Pàmies, Joan |
dc.date | 2014 |
dc.identifier.citation | Rodriguez, R.; Arumi, D.; Figueras, J. Post-Bond test of through-silicon vias with open defects. A: IEEE European Test Symposium. "PROCEEDINGS 19TH IEEE EUROPEAN TEST SYMPOSIUM". Paderborn: 2014, p. 1-6. |
dc.identifier.citation | 978-1-4799-3414-0 |
dc.identifier.citation | 10.1109/ETS.2014.6847816 |
dc.identifier.uri | http://hdl.handle.net/2117/24629 |
dc.language.iso | eng |
dc.relation | http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6847816 |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats |
dc.subject | Integrated circuits--Design and construction |
dc.subject | Integrated circuits--Testing |
dc.subject | 3-D IC |
dc.subject | Through-Silicon Via (TSV) |
dc.subject | resistive open defect |
dc.subject | TSV testing |
dc.subject | duty cycle |
dc.subject | design for testability |
dc.subject | Circuits integrats digitals -- Disseny i construcció |
dc.subject | Circuits integrats -- Testeig |
dc.title | Post-Bond test of through-silicon vias with open defects |
dc.type | info:eu-repo/semantics/publishedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
dc.description.abstract |