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dc.contributor | Nemirovsky, Mario |
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dc.contributor | Moreto Planas, Miquel |
dc.contributor.author | Roca Marí, Damián |
dc.date | 2014-07-01 |
dc.identifier.citation | 100728 |
dc.identifier.uri | http://hdl.handle.net/2099.1/22855 |
dc.language.iso | eng |
dc.publisher | Universitat Politècnica de Catalunya |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject | Computer architecture |
dc.subject | Simulació |
dc.subject | Teoria de cues |
dc.subject | Metodes estadístics |
dc.subject | Processador |
dc.subject | Arquitectura de Computadors |
dc.subject | Simulation |
dc.subject | Queue models |
dc.subject | statistical methods |
dc.subject | processor |
dc.subject | computer architecture |
dc.subject | Arquitectura d'ordinadors |
dc.title | High level queuing architecture model for high-end processors |
dc.type | info:eu-repo/semantics/masterThesis |
dc.description.abstract |