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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
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dc.contributor | Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors |
dc.contributor.author | Rana, Manish |
dc.contributor.author | Canal Corretger, Ramon |
dc.date | 2014 |
dc.identifier.citation | Rana, M.; Canal, R. SSFB: a highly-efficient and scalable simulation reduction technique for SRAM yield analysis. A: Design, Automation and Test in Europe. "Design, Automation and Test in Europe: proceedings: Dresden, Germany: March 24-28, 2014". Dreden: European Interactive Digital Advertising Alliance (EDAA), 2014, p. 1-6. |
dc.identifier.citation | 978-398153702-4 |
dc.identifier.citation | 10.7873/DATE2014.045 |
dc.identifier.uri | http://hdl.handle.net/2117/23209 |
dc.language.iso | eng |
dc.publisher | European Interactive Digital Advertising Alliance (EDAA) |
dc.relation | http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6800246 |
dc.rights | Attribution-NonCommercial-NoDerivs 3.0 Spain |
dc.rights | info:eu-repo/semantics/openAccess |
dc.rights | http://creativecommons.org/licenses/by-nc-nd/3.0/es/ |
dc.subject | Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats |
dc.subject | Àrees temàtiques de la UPC::Matemàtiques i estadística::Probabilitat |
dc.subject | Integrated circuits |
dc.subject | Probabilities |
dc.subject | Monte Carlo methods |
dc.subject | SRAM chips |
dc.subject | Failure analysis |
dc.subject | Integrated circuit yield |
dc.subject | Iterative methods |
dc.subject | Probability |
dc.subject | Circuits integrats |
dc.subject | Probabilitats |
dc.title | SSFB: a highly-efficient and scalable simulation reduction technique for SRAM yield analysis |
dc.type | info:eu-repo/semantics/publishedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
dc.description.abstract | |
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