Embedded and DSP design tools integration for Xilinx FPGA development

Abstract

The aim of this projecte de final de master is to design a firmware with VHDL and the Matlab System Generator for Xilinx DSP of a test application, which mixes several of the Xilinx tools to create the design. The target FPGA is a Spartan 6 from a SP605 test board. In addition, this memory contains the main characteristics of the firmware design, a description of the tools used and the methodologies available to create the Firmware. Furthermore, it provides some theoric background and in some cases, it is useful as a guide to implement a similar solution to the one proposed. Furthermore, there is a description of the findings in the System Generator design field and also with the interaction in the Xilinx FPGA design flow. There have been described the tests which were performed to ensure the correctness of the design.